A Systolic LRU Processor and Its Top-Down Development

We present a novel systolic processor that implements the least-recently-used (LRU) policy for multi-level storage systems. The design is developed by successively reening a high-level description of the algorithm. The eeect of varying the degree of pipelining on performance is discussed. We also show how the design methodology used for the LRU processor can be applied to the development of other systolic systems.